Regarding methods of fabrication of thin film transistors (TFT) used as the active elements in liquid crystal displays, from the viewpoint of devising the increase of surface area and the reduction of cost, low-temperature processes and the use of inexpensive glass substrates are desirable. In such a low-temperature process, it is necessary to be able to form large-grain polysilicon films that are equivalent to those of high-temperature processes, and to activate the impurities sufficiently. Further, it is important to be able to form high-quality gate insulation films having a film quality equal to or greater than thermal oxide films.
As technology for forming gate insulation films at low temperatures, there have been from the past film formation methods such as atmospheric-pressure CVD method, low-pressure CVD method, ECR-CVD method and the like. Atmospheric-pressure CVD method and low-pressure CVD method are high in productivity, but the film quality as gate insulation films is inferior. For example, there are such problems as the increase of the space charge and surface charge in silicon oxide films, the degradation of the properties of the current at on state, the degradation of the properties of the leakage current at off state, and the shift of the threshold voltage of TFTs. Also, in the ECR-CVD method, the film quality is comparatively good, but there is a problem that the productivity is markedly low, and all of the prior film formation methods do not satisfy the conditions for film formation of gate insulation films of TFT used for the active elements of liquid crystal displays.
Also, as a low-temperature process for forming silicon oxide films, other than the above-mentioned film formation methods, there is also the plasma-enhanced chemical vapor deposition method (plasma CVD method). The plasma CVD method is a film formation method whereby a film is formed by causing a discharge in a feed gas within a reaction chamber by applying a high frequency electric power between electrodes, and causing a reaction to break down the feed gas with the plasma formed thereby. Because such a film formation method has the advantages of a high deposition rate of film, a low stress applied to the substrate, a good step coverage, and the like, it has been used up to the present for the formation of interlevel insulator film of semiconductor integrated circuits. Also, as published in Sharp Giho (Sharp Technical Journal) (No. 61, April 1995), it is coming to be seen as a film formation method for forming gate insulation films of TFT as well. The conditions of the plasma CVD method examined here are that the distance between electrodes for generating the plasma is within the range of 35 mm to 65 mm, and the pressure inside the reaction chamber is in the range of 800 mtorr to 1200 mtorr, and conditions having exceeded such ranges are not suitable for forming gate insulation films of TFT. Such is suggested in Sharp Giho, and others. The properties of film formation have been evaluated within the scope of such conditions because in addition to the space charge inside a silicon oxide film occurring more easily as the distance between the electrodes is made smaller, an surface state is generated more easily on the surface of a semiconductor film in contact with the silicon oxide film. Furthermore, the properties of the current at on state and leakage current at off state of the TFT trend to be degraded due to the presence of a surface charge originating in this surface state. Further the properties have been evaluated within the scope of conditions mentioned above, because the properties of the current at on state and leakage current at off state of the TFT tend to be degraded more as the pressure inside the reaction chamber is lowered more.
However, the plasma CVD method has not arrived at the point where it genuinely can be applied to a gate insulation film of TFT formation process as examined by changing various parameters within the above-mentioned scope of conditions. This is because when forming a gate insulation film of TFT, which is different from depositing a silicon oxide film on a comparatively narrow substrate such as a silicon wafer as a interlevel insulator film, not only is the deposition rate of film high, the stress applied to the substrate low, and the step coverage satisfactory, but there are additional conditions inherent to this field. Namely since a gate insulation film of TFT is being formed, the electrical properties related to the space charge and surface state of the aforementioned silicon oxide film must be satisfactory. Moreover, it is desirable to be able to form evenly and at high speed a silicon oxide film on the entirety of a large-surface area substrate being 360 mm.times.465 mm, such as an active matrix of a liquid crystal display panel. However, by only applying the film formation conditions used in the formation of interlevel insulator film of semiconductor integrated circuits to the formation of gate insulation films of TFT, the conditions mentioned above cannot be satisfied.
For example, following conditions are set when forming a silicon oxide film under the conventional technology in plasma CVD method: the distance between electrodes is 35 mm, the pressure in the reaction chamber is 1500 mtorr, and the TEOS gas flow is 30 SCCM or less. Setting the film formation conditions from the viewpoint of obtaining a silicon oxide film having satisfactory electrical properties related to the space charge and the surface state, not only causes the deposition rate of film to drop markedly to about 250 Angstrom/minute, if the value obtained from Equation (1) by the evaluation method explained below, which is expressed in terms of deviation of the film thickness, but also causes the result to be extremely high, being about 20% higher. Here, to be genuinely applicable to the formation process of a gate insulation film of TFT, it is necessary to secure a deposition rate of film of 700 Angstrom/minute or more, and to suppress deviation of the film thickness to 7% or less.
In consideration of such problems, the object of the present invention is to provide a TFT fabrication method, being a low-temperature process, that can form a film at a high speed and have an even film thickness across a large-surface area substrate to produce a high-quality gate insulation film having satisfactory charge behavior. A deposition rate of a film can be increased.